Memory devices, such as dynamic random access memory (“DRAM”) devices are generally characterized by several parameters, the most important of which is their storage capacities. The storage capacity of a memory device is generally expressed as a number of bits or bytes, such as a 256 megabit (“Mb”) memory device. Generally, data can be read from and written to a memory device having a specific capacity in a variety of configurations. In each configuration, each column address accesses a specific number of bits. For example, data can be read from and written to a 512 Mb memory device in the form of 128 million “nibbles” each consisting of 4 bits (128 Meg×4 bits=512 Mb), 64 million “bytes” each consisting of 8 bits (64 Meg×8 bits=512 Mb), or 32 million “words” each consisting of 16 bits (32 Meg×16 bits=512 Mb). In the 128 Meg×4 configuration, 4 bits are accessed by each column address. In the 64 Meg×8 configuration, 8 bits are accessed by each column address. Finally, in the In the 32 Meg×16 configuration, 16 bits are accessed by each column address. The manner in which the memory device must be addressed will therefore differ depending upon the configuration selected. The addressing requirements for each of the above-described configurations of the 512 Mb memory device is shown in the following Table 1:
TABLE 1128 Meg × 464 Meg × 832 Meg × 16Configuration32 Meg × 4 ×16 Meg × 8 ×8 Meg × 16 ×4 banks4 banks4 banksRow Addressing8 K (A0-A12)8 K (A0-A12)8 K (A0-A12)Bank Addressing4 (BA0, BA1)4 (BA0, BA1)4 (BA0, BA1)Column Addressing4 K (A0-A9,2 K (A0-A9,1 K (A0-A9)A11, A12)A11)
It can be seen from the above Table 1 that the row and bank addressing remains the same regardless of the configuration selected. However, since the number of bits accessed for each column address varies with the selected configuration, the number of column addresses, and hence the required number of column address bits, varies with the selected configuration. For the 128 Meg×4 configuration, there are 4,000 column addresses requiring 12 column address bits, for the 64 Meg×8 configuration, there are 2,000 column addresses requiring 11 column address bits, and for the 32 Meg×16 configuration, there are 1,000 column addresses requiring 10 column address bits.
The addressing requirements for corresponding configurations for a proposed 1024 Mb memory device is shown in the following Table 2:
TABLE 2256 Meg × 4128 Meg × 864 Meg × 16Configuration64 Meg × 4 ×32 Meg × 4 ×16 Meg × 4 ×4 banks4 banks4 banksRow Addressing16 K (A0-A13)16 K (A0-A13)16 K (A0-A13)Bank Addressing4 (BA0, BA1)4 (BA0, BA1)4 (BA0, BA1)Column Addressing4 K (A0-A9,2 K (A0-A9,1 K (A0-A9)A11, A12)A11)
As can be seen from Table 2, the addressing requirements for a 1024 Mb memory device are identical to the addressing requirements for the 512 Mb memory device except that the 1024 Mb memory device has twice as many row addresses (16k rather than 8k) and thus requires an additional row address bit, i.e., 14 row address bits rather than just 13 row address bits.
Unfortunately, a single chip 1024 Mb memory device is not currently available. However, it would be desirable to meet the current demand for a single chip 1024 Mb memory device by combining two of the 512 Mb memory devices in a single package and operating them in combination. However, it does not seem possible to combine the 512 Mb memory devices in this manner because of the different addressing requirements of the 1024 Mb memory devices compared to the 512 Mb memory devices. More specifically, the 512 Mb memory devices could be accessed in a conventional manner by simply adding an extra column address bit. However, there are at least two reasons why this approach is not feasible. First, the need to operate the 1024 Mb memory device in different configurations means that the column address bits required will vary with the selected configuration. Second, as explained above, 14 row address bits (i.e., A0-A13) will be applied to the 1024 Mb memory device, but the 512 Mb memory devices used to implement the 1024 Mb memory device can use only 13 row address bits (i.e., A0-A12). Therefore, it does not seem feasible to implement a 1024 Mb memory device using two the 512 Mb memory devices, particularly in view of the need to operate the 1024 Mb memory device in various configurations.
The problem of implementing higher capacity memory devices by combining multiple lower capacity memory devices has been discussed in the context of implementing a 1024 Mb memory device by combining two 512 Mb memory devices. However, the same or similar problems exist in combining more than 2 lower capacity memory devices to provide a higher capacity memory device as well as in combining memory devices having storage capacities other than 512 Mb.
There is therefore a need for a memory device and method that provides a relatively large storage capacity obtained by combining several smaller capacity memory devices and still allows the memory device to be operated in a variety of configurations.